Pulse train repetition rate divider that divides by n+1/2 where n is a whole number



3,18Q,832 ES .BY N+ 5 June 15, 1965 c. w. PUGH PULSE TRAIN REPETITION RATE DIVIDER THAT DIVID WHERE N IS A WHOLE NUMBER 2 Sheets-Sheet 1 Filed Sept. 18, 1962 OUTPUT INPUT PULSES TO BE D/V/DED SET INPUT FIG. 3

NUMBER B/NARVNUMBER /MAL //v l/EN TOR C. W PUGH A r TORNEV June 15, 1965 PULSE TRAIN REPETITION RATE DIVIDER THAT DIVIDES BY N+ Filed Sept. 18, 1962 WHERE N IS A WHOLE NUMBER H l I 2 Sheets-Sheet 2 INVENTOR C. W. PUGH ATTORNEY PULSE TRAIN REPETITION RATE DlViDER THAT DIVIDES BY N /2 WHERE N IS A WHOLE NUMBER Charles W. Pugh, Burlington, N.C., assignor, to Bell Telephone Laboratories, Incorporated, New York, N.Y., a corporation of New York Filed Sept. 18, 1962, Scr. No..224,567 4 Claims. (Cl. 328-42) This invention relates to pulse train repetition rate di- United States Patent O 7 viders and in particular to' such dividers which divide by numbers other than whole numbers.

The use of pulse train repetition rate dividers in digital types of apparatus is well known.

They are frequently used, for example, to produce timing pulse trains having repetition rates which are submultiples of the repetition rates of basic timing or clock pulse trains. It appears, however, that such dividers found in the prior art are limited to dividing by whole numbers. In other words, pulse trains produced by prior art dividers have repetition rates which are equal to the repetition rates of input pulse trains divided by whole numbers. Although these dividers are useful in many applications, they cannot, of course, divide by a number other than a whole number.

An object of the invention is to produce a pulse train having a' re etition rate which is equal to the repetition rate of another pulse train divided by N+ /2, where N is'a whole number.

In accordance with the invention in one of its broader aspects, a pulse train'is applied to a counter. One-half of a pulse cycle after a predetermined count is registered in the counter anfoutput signal is produced. When the output-signal is produced, the counter is reset to a second count which is less than the predetermined count by an amount equal to 2N+1, where N is a whole decimal number. When the counter registers a third count equal to the second count plus N 1, another output signal is produced and the cycle repeats itself. These output signa-ls appear at a repetition rate which is equal to the ropetition rate of the pulse train divided by N /2.

The invention is'disclosed and claimed as comprising incremental counters. It should be recognized, however, thatit is a' matter of convention as to whether a particular counter is considered to be of the incremental type or of the decremental type. In other words, it is a matter of convention as'to whether successive outputs from a particular counter" correspond to an increasing set of numbers or a decreasing set of numbers. In view of this fact, the counters referred to in the present disclosure and claims also include those that may nominally be referred to as of the decremen-tal type. I

One embodiment of the invention includes a counter having both a presetting circuit which, when energized, causes the-counter to registera preset value and an input circuit for receiving'an input pulse train. An AND gate is connected to both the output and the input circuits of the counter to produce a first output signal at substantially one half of a pulse period of the input pulse train after the counter registers a predetermined count. This output ignal is applied both to the counter for setting the counter t-o'register'a second count which is 2N+l less than the predetermined count and to an OR gate, A second AND gate is connectedto both the input and the output circuits of the counter to produce a second output signalwhen the counter registers a third count which equals the second count plus N+1. The output signal from the second AND gate is :also appliedv to the OR gate. The output signals from the OR gate are made available at an output terminal as the output pulse train of the divider.

3,189,832 Patented June 15, 1965 FIG. 1 shows a block diagram of one embodiment illustrating the principles underlying the invention;

FIG. 2 illustrates waveform of pulses appearing at.vari-, ous points within the embodiment of FIG. 1 when this embodiment is in operation; and a FIG. 3 illustrates a conventional conversion between binary and decimal numbers.

The embodiment of FIG. 1 includes a conventional three-stage counter. The first stage comprises a steering circuit 16 and a flip-flop circuit 11, the second stage comprises a steering circuit 12 and a flip-flop circuit 13 while the third stage comprises a steering circuit 14 and a flipflop circuit 15. These circuits are conventional in both design and operation so that a positive-going pulse applied to any of the steering circuits causes its flip-flop circuit to change state. To facilitate the following discussion, the convention of identifying the halves of the flip-fiop circuits by zeros and ones has been adopted. The stages are interconnected so that the output identified as E of the zero half of flip-flop circuit 11 is applied to steering circuit 12 while the output identified as E of the zero half of flip-flop circuit 13 is applied to steering circuit 14. An input lead 16 applies an input identified as b to steering circuit 11}. Finally, a set lead 17 is pro- 'vi-ded for applying a signal to the one sides of the flipflop circuits to cause the outputs identified as c,'d and e from these sides to be at their less positive values and the outputs identified at 5, Z and a to be at their more positive values.

The embodiment of FIG. 1- also includes a circuit arrangement comprising an AND gate 18, an inverter circuit 1? and a pulse regenerator Zti. The input circuit of inverter circuit 19 is connected to input lead 16 while its output circuit, on which appears an output identidied as '5, is connected to one of the input circuits of AND gate '18. econd and third input circuits of AND gate 18 are connected to the output circuits of the zero sizes of flip-flop circuits 1 1 and 13, respectively, while a fourth input circuit of AND gate 18-is connectedto'the output circuit of the one side of fiip-fiop circuit 15. The output circuit of AND gate 18, on which appears an output identified as f, is connected to the inputcircuitof pulse regenerator 20. The output circuit of regenerator 20 is connected .to input circuits of the zero side of fiip flop circuits 11 and an OR gate'21. A pulse applied to flip-flop circuit 11 by regenerator 20 causes output 5 to switch to its less positive value while output c is switched to-its more positive value.

'The embodiment of FIG. 1 also includes an AND gateZZ. The input circuits of AND gate 22 are connected to input lead 16, the output circuit of the. one side of flip-flop circuit 11 and the output circuits of the zero sides of flip-flop circuits 13 and 15, respectively. The output circuit of AND gate 22 is connected to a second input circuit of OR gate 21.v The output from the embodiment appears on an output load 23'connected to the output circuit of OR gate 21.

AND gates 13'and 22 produce more positive outputs when all'of their inputs are at their more positive levels.

The operation of the embodiment of FIG. 1 is now pre-' sentedlin conjunction with the various waveforms shown in FIG. 2.- These waveforms, which all have the same' snsaesa positive levels while outputs E, d and E are at their more positive levels. At time t the first pulse of an input pulse train is applied to input lead 16 as input I). The first positive-going excursion of input 1) causes flip-flop circuit 11 to change state so that output switches to its more positive value and output switches to its less positive value. Steering circuit 12 does not respond to the change in output 5 because, as previously discussed,

the steering circuits only respond topositive-going signals.

Flip-flop circuits 13 and do not, therefore, change state. As soon as flip-flop circuit 11 changes state, all of the inputs (1;, c, d and 5) applied to AND gate 22 are at their more positive levels and AND gate 22 produces a positive-going output which is applied via OR gate 21 to output lead 23 as output 9. When input I) undergoes a negative-going change one-half of a pulse period later, output 5/ undergoes a negative-going excursion which results in producing an output pulse. Nothing else undergoes a change at this time other than output 3.

At time 1 input I; undergoes a positive excursion which causes flip-flop circuit 11 to change state. When flip-flop circuit 11 changes state, output 0 switches to its less positive value while output 5 switches to its more positive value. Steering circuit 12 responds to the positive-going change in output '6 and causes flip-flop circuit 13 to change state. When flip-flop circuit 13 changes state, output (I switches to its more positive value while output 5 switches to its less positive value. Because steering circuitld does not respond to the negative-going change in output 3 flip-flop circuit 15 does not change state. The inputs applied to AND gates 18 and 22 are not at this time of such a nature to cause either of their outputs to change. Input 1) and inverter output 3 again undergo achange one-half of a pulse period later; nothing else occurs, however, until time t The positive-going excursion of input 0 at time t again causes flip-flop circuit 11 to change state. When flip-flop circuit 11 changes state, output 0 switches to its.

more positive value while output 5 switches to its less positive value. Because steering circuit 12 does not respond to a negative-going change in output 5, neither of flip-flop circuits 13 and 15 changes state. Other than input b and inverter output 5 again undergoing a change one-half of a pulse period later, nothing else occurs until time [4.

At time 22;, input b once again undergoes a positive excursion which again causes flip-flop circuit 11 to change state. This latest change in flip-flop circuit 11 causes its output 0 to switch to its less positive value while its outi put 5 switches to its more positive value. Steering circuit 12 responds to the positive-going change in output 5 and flip-flop circuit 13 changes state. When flip-flop circuit 13 changes state, its output d switches to its less positive value while its output 3 switches to its more positive value. Steering circuit 14 responds to the positive-going change in output I? and causes flip-flop circuit 15 to change state. When flip-flop circuit 15 changes state, its output 0 switches to its more positive value white its output i5 switches to its less positive value.

At this time, outputs E, E and 0 applied to AND gate 18 are at their more positive levels while inverter output 5 applied to AND gate 18 is at its less positive level. At time t which is one-half of a pulse period after timev t inverter output 5 changes to its more positive value and AND gate 18 produces an output which triggers pulse regenerator 24;. The output from regenerator is unaffected by output 1 once regenerator 20 has been triggered. Regenerator 2% produces a pulse output which has a duration substantially eq ral to the duration of the pulses in input I).

The output from regenerator 20 is applied to flip-flop circuit 1-1 and causes this circuit to change state so that 5 experiences a negative-going excursion at this time, steering circuit 1?. does not respond to output 5 and flipfiop circuits 13 and 15 remain in the states which they were in at time 1 When output 5 switches to its less positive value, output 1 of AND gate 18 reverts to its less positive level. Output 1, as shown in FIG. 2, is a relatively short pulse or spike.

The output from regenerator 2% is also applied to OR gate 21, which causes a second pulse to appear in output 9 as shown in FIG. 2. It should be noted that the leading edge of this pulse occurs at three and one-half pulse periods of input I) after the leading edge of the preceding pulse in output g.

At time t input I) undergoes another change which causes flip-flop circuit 11 to changestate. Output 5 change state. change state. Flip-flop circuit 15 again changes state at time 2%; while flip-flop circuits 13 and 15 do not change state.

At time i flip-flop circuits 11, 13 and 15 each change state. The flip-flop circuits are now all in the same states in which they were prior to time t At time t the cycle that took place between times 1 and t begins again.

A comparison of output g with input b will immediately indicate that the repetition rate of output g is equal to the repetition rate of input 12 divided by three and onehalf.

The operation of the embodiment of FIG.-1 may be further appreciated by conside-ringpoutputs c, d and e as representing binary bits of binary numbers. In particular, let the less positive values of these outputs represent binary zeros and their more positive values represent binary ones. The table in FIG. 3 showsa conventional conversion between the binary numbers represented by outputs c, d and e and decimal numbers. It will be Flip-flop circuit 15, however, does not noted that, in accordance with this convention, the counter registers the binary equivalent of the decimal four at time 12;. One-half of a pulse period after, the binary equivalent of the decimal four has been registered, an output is produced and the counter is reset to the binary equivalent of the decimal minus three. Minus three, it should be noted, is 2N +1, or seven, less than the four. (Because the counter resets to the binary equivalent of the decimal zero in the next count after the binary equivalent of the decimal seven, the binary equivalent of the decimal minus three'is also the binary equivalent of the decimal five.) At time t (which is three and one-half pulse periods after time t the. counter registers the binary equivalent of the decimal oneand another output pulse is produced, One, it should be noted, is N +1, or four, greater than minus three. The cycle then repeats itself with output pulses appearing in output g at a repetitron rate equal to the repetition rate of input 17 divided by N+ /2 which is three and one-half.

Although the invention has been disclosed with respect to one embodiment, various other embodiments may be devised by those skilled in the art without departing from the spirit and scope of the invention.

What is claimed is: V V 1. A pulse train repetition rate divider that divides by N+ /z, where N is a whole number, comprising a pulse counter, a an inputcircuit connected to said pulse counter for applying input pulsesthereto,

first means connected to the output of said input circuit and the output of said counter to produce a first output signal only upon the termination of one-half of a pulse period of said input pulses after said counter registers a first count equal to N greater than the initial count in said counter,

second means to apply said, first output signal to said counter to reset said counter'to a second count.

5 which is less than said first count by an amount equal to 2N+ 1,

third means responsive to said counter to produce a second output signal when said counter registers a third count which is greater than said second count by an amount equal to N 1, and

fourth means making available said first and second output signals as the output of said combination.

2. A combination comprising the combination of claim 1 and a presett-ing circuit for setting said counter to a count one less than said third count.

3. A combination in accordance with claim 1 in which said first means comprises a first AND gate having its input leads connected to said counter and said input circuit and a pulse regenerator having its input circuit connected to the output circuit of said AND gate,

6 said third means comprises a second AND gate having its input leads connected to said counter and said input circuit, and said fourth means comprises an OR gate having its input circuits connected to the output circuits of said pulse regenerator and said second AND gate, respectively. 4. A combination comprising the combination of claim 3 and a presetting circuit for setting said counter to a count one less than said third count.

References Cited by the Examiner UNITED STATES PATENTS 3,012,096 12/ 6 1 Steinmetz et a1. 307-885 ARTHUR GAUSS, Primary Examiner. 

1. A PULSE TRAIN REPETITION RATE DIVIDER THAT DIVIDES BY N+1/2, WHERE N IS A WHOLE NUMBER, COMPRISING A PULSE COUNTER, AN INPUT CIRCUIT CONNECTED TO SAID PULSE COUNTER FOR APPLYING INPUT PULSES THERETO, FIRST MEANS CONNECTED TO THE OUTPUT OF SAID INPUT CIRCUIT AND THE OUTPUT OF SAID COUNTER TO PRODUCE A FIRST OUTPUT SIGNAL ONLY UPON THE TERMINATION OF ONE-HALF OF A PULSE-PERIOD OF SAID INPUT PULSES AFTER SAID COUNTER REGISTERS A FIRST COUNT EQUAL TO N GREATER THAN THE INITIAL COUNT IN SAID COUNTER, SECOND MEANS TO APPLY SAID FIRST OUTPUT SIGNAL TO SAID COUNTER TO RESET SAID COUNTER TO A SECOND COUNT WHICH IS LESS THAN SAID FIRST COUNT BY AN AMOUNT EQUAL TO 2N+1, THIRD MEANS RESPONSIVE TO SAID COUNTER TO PRODUCE A SECOND OUTPUT SIGNAL WHEN SAID COUNTER REGISTERS A THIRD COUNT WHICH IS GREATER THAN SAID SECOND COUNT BY AN AMOUNT EQUAL TO N+1, AND FOURTH MEANS MAKING AVAILABLE SAID FIRST AND SECOND OUTPUT SIGNALS AS THE OUTPUT OF SAID COMBINATION. 